Integrated Ccuit Design

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Dorethea R


Date added:

April 21, 2015








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6 / 1441


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A three-bit dynamic latch contains 3 non-inverting dynamic latch cells made by using the ECIF buildings block at mask level within Chipwise. So I will start by building the one-bit latch… One-Bit Latch The output graph should look a little like this… So If I recreate this circuit as a STX diagram in Chipwise I get the following… So I check for errors and if all clear I can proceed to generate my ECIF diagram… With the ECIF diagram generated I need to extract and run DRC to test for any errors...
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I will also need to set the vdd to 5V and initialize the output to 0V. You can see that this simulation has probes on the input output clock 1 and clock 2. The simulation has a run time of 400ns sampling every 2ns. Below shows the result from simulating… You can see that the outputs are correct and look almost identical to my predicted graph...
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